The present invention relates to a current amplifier for doubling a current and a current mode type analog/digital converter using the same.
As one of analog/digital converters (to be referred to as A/D converters hereinafter), a current mode pipe line type A/D converter is known. The conventional current mode pipe line type A/D converter is constituted by pipe-line-connecting n stages of unit A/D converters called bit cells.
Each bit cell is constituted by a current mirror circuit and a current comparator. An input current is compared with a reference current. The doubled current or a current obtained by subtracting a reference current from this doubled current is output on the basis of the comparison result.
More specifically, the comparison result from the current comparator is output from the digital data output terminal as a 1-bit digital output, and simultaneously, a residual current obtained by subtracting the 1-bit quantized output from the input current is output to the next bit cell as an output current. Such bit cells are pipe-line-connected in n stages to perform n-bit A/D conversion.
To double the input current, the input-to-output current ratio of the current mirror circuit constituted by three transistors is used. This input-to-output current ratio is defined by the ratio of the area of one transistor of the current mirror circuit to the sum of the areas of the remaining two transistors. However, since transistor sizes vary due to manufacturing variations or the like, the input-to-output current ratio of the current mirror cannot be accurately 2. The accuracy of the input-to-output current ratio directly affects the conversion accuracy, so the same accuracy as the desired conversion accuracy is required. When A/D converter is realized using an IC, the relative accuracy of the transistor is roughly 1%. For this reason, the conversion accuracy is substantially limited to 7 bits. If the conversion accuracy is to be increased in this arrangement, the accuracy of devices such as transistors constituting the current mirror circuit must be increased. For this purpose, an expensive process or trimming is required, resulting in an expensive A/D converter.
To increase the conversion accuracy of the current mode pipe line type A/D converter, the current mirror for doubling the input current may be constituted by a switched current mirror. In the switched current mirror, the input current is sampled and held by two current sample/hold circuits, the hold outputs are added to double the input current, and this current is sampled and held by the third current sample/hold circuit and output. According to this technique, a current amplification factor of 2 can be obtained independently of the ratio of transistor sizes, so improvement of the conversion accuracy of the A/D converter can be expected.
In this technique, however, the current sampling/holding operation must be performed twice to double the current: sampling/holding of the input current and sampling/holding the doubled current. For this reason, the current sample/hold circuits must be operated with a clock frequency twice the bit cell, and in other words, at a period 1/2 the conversion period of the A/D converter. The circuit must be operated at a higher speed. In high-speed A/D conversion, the input current can hardly be properly sampled and held due to the transient response of the circuit, and the conversion accuracy of the A/D converter cannot be so largely improved.
Generally, to form an A/D converter into an IC, a differential circuit is used to minimize the influence of noise from the digital system. When the above-described current sample/hold circuit has a differential arrangement, the common mode component of a differential current must be properly canceled. If the common mode component cannot be completely canceled, the current of the common mode component is also doubled, and accordingly, the output current is saturated. If the common mode component is nonuniformly corrected for the positive and negative phases of the differential current, the nonuniform component is added to the differential output current as a differential current component. This results in an error in differential output current, and consequently, a conversion error of the A/D converter.
However, when the common mode component is to be canceled using the current mirror, matching between the positive- and negative-phase currents depends on matching of transistor sizes of the current mirror, as described above. The common mode component cannot be uniformly corrected for the positive and negative phases of the differential current, so the current of the common mode component is difficult to accurately cancel.
As described above, in the conventional current mode pipe line type A/D converter, the conversion accuracy is directly influenced by manufacturing variations of transistors. When a switched current mirror is used to avoid this problem, the operation speed of the circuit is doubled, and accordingly, the conversion accuracy degrades due to the transient response, or power consumption increases. When a differential arrangement is employed to minimize the influence of noise from the digital system, the common mode component must be accurately canceled although this can hardly be realized.